We embark on a adventure through the first months of the Monero Hardware team's work towards designing a hardware wallet, showcasing several generations of devices as well as illustrating the firmware, host software, enclosure, and other project efforts completed or underway.
A state of the project is explained in this interactive (demonstration rich) presentation, in which real Monero hardware wallets are passed out for hands on inspection.
In this hour, we showcase the march of progress leading to the first Monero Hardware Wallet release.
While considering what qualities existing hardware wallet technology often provides, we at Monero Hardware illustrate a fresh new design including a secure element unencumbered by NDA (nondisclosure agreement) terms. We show and explain other unique features as well, arising from a well documented set of requirements.
Proceeding, we consider attack vectors including decapsulation, electron and voltage contrast microscopy, side channel glitching and correlation power analysis, as well as potting compound removal and run of the mill hypodermic needle tapping of serial bus lanes.
Continuing with hardware design, we review the workflow designers and layout engineers follow while creating an experimental circuit. We reflect on the six month project and it's unique distribution and test process as well as strong community ties supported by the communication and documentation we've chosen to emphasize. Lastly, we explain the production of a hardware wallet device from print to assembly and even demonstrate a rapid prototyping hardware run to produce a single board (components and all) live.
Prototype history
Nullboard
Julian Candy
...others
Demonstration: On camera functional state
PCB formats
Developer edition
Consumer edition
Naming convention
Breakneck
Monezor
Ledgour
Requirements
Whirlwind review
Agile methodology
Secure elements
State of market availability
Contrast with secure enclave
Contrast with hardware security module
Demonstration: JTAG firmware dump
Review of contending hardware secure logic
