Verilog Synthesis and more with Yosys

Clifford Wolf

At 32C3 I presented a free and open source verilog to bitstream flow for iCE40 FPGAs. This flow consists of Yosys (Verilog Synthesis), Arachne-pnr (Place and Route), and Project IceStorm (Low-level tools and FPGA reverse engineering).

This talk has a wider focus and discusses various applications of Yosys, i.e.:

Synthesis:
- ASIC Synthesis
- FPGA Synthesis for iCE40 FPGAs (complete flow)
- FPGA Synthesis for Xilinx 7-Series FPGAs
- Synthesis to simple Verilog or BLIF files

Formal Verification:
- Property checking with build-in SAT solver
- Property checking with ABC using miter circuits
- Property checking with yosys-smtbmc and SMT solvers
- Formal and/or structural equivalence checking

I also briefly discuss Open Source tools for related topics, such as Verilog simulation and SAT/SMT solving.

Related

Download

Embed

Share:

Tags