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RSS, last 100
Podcast feed of the last two years
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Podcast audio feed of the last year
Podcast archive feed, everything older than two years
SD quality
Search for person "Clifford"
52 min
Formal Verification of Verilog HDL with Yosys-SMTBMC
52 min
2016-12-28
976
Clifford
33C3: works for me
59 min
A Free and Open Source Verilog-to-Bitstream Flow for iCE40 FPGAs
59 min
2015-12-27
22705
Clifford
32C3: gated communities
35 min
Python Gradual Typing: The Good, The Bad and the Ugly
Talk
BOB
35 min
2022-03-11
81
Ben Clifford
BOB Konferenz 2022
113 min
Verilog Synthesis and more with Yosys
113 min
2016-03-25
531
Clifford Wolf
Easterhegg 2016
46 min
The nextpnr FOSS FPGA place-and-route tool
the next step forward in open source FPGA tools
46 min
2018-12-28
875
Clifford Wolf
35C3: Refreshing Memories
29 min
End-to-end formal ISA verification of RISC-V processors with riscv-formal
29 min
2017-12-27
1486
Clifford Wolf
34C3: TUWAT