Search for person "Clifford"

A Free and Open Source Verilog-to-Bitstream Flow for iCE40 FPGAs
59 min

A Free and Open Source Verilog-to-Bitstream Flow for iCE40 FPGAs

32C3: gated communities
Formal Verification of Verilog HDL with Yosys-SMTBMC
52 min

Formal Verification of Verilog HDL with Yosys-SMTBMC

33C3: works for me
Verilog Synthesis and more with Yosys
113 min

Verilog Synthesis and more with Yosys

Easterhegg 2016
Python Gradual Typing: The Good, The Bad and the Ugly
35 min

Python Gradual Typing: The Good, The Bad and the Ugly

BOB Konferenz 2022
The nextpnr FOSS FPGA place-and-route tool
46 min

The nextpnr FOSS FPGA place-and-route tool

the next step forward in open source FPGA tools

35C3: Refreshing Memories
End-to-end formal ISA verification of RISC-V processors with riscv-formal
29 min

End-to-end formal ISA verification of RISC-V processors with riscv-formal

34C3: TUWAT