May Contain Hardware Acceleration: Building a 3D Graphics Accelerator in FPGA for the MCH2022 Badge
The MCH2022 Badge is an wonderful piece of hardware, with a great screen, a dual-core ESP32 CPU, and an Lattice FPGA to act as a co-processor. What if we could use the power of the FPGA to render 3D graphics? In this talk I'll take you through the basics of 3D rendering, the challenges of doing this on the Badge, and how I made the little Lattice produce pretty polygons.
I don't know about you, but when I get my hands on a piece of hardware with a lovely screen and a bit of processing power, my first thought is "Can I make this produce 3D graphics?" (Well, the *real* first question is "Can it run Doom?" but that was already answered by the wonderful Sylvain Lefebvre.) So when the MCH2022 Badge was announced to come with an FPGA to play around with, well I knew where my free time would end up for a while.
The FPGA on the MCH2022 badge is, to put it mildly, *petite* at just 5K LUTs. And while it has plenty of memory space, memory bandwidth is limited. A traditional framebuffer-based 3D renderer wasn't going to work. So I had to get creative and instead render in vertical strips, while using as few operations per pixels as possible.
In this talk I'll explain how rasterization (the process of turning triangles into pixels) typically works, why this is challenging to do on the Badge hardware, and what I did instead. I'll talk about texturing and I'll add some crunchy digital details like memory bandwidth.
Licensed to the public under https://creativecommons.org/licenses/by/4.0/